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| INIC-1608 initio corporation 1 INIC-1608 usb to sata bridge specification version 1.0 august 10, 2007 initio corporation
INIC-1608 initio corporation 2 change history: create on 07/06/2007. INIC-1608 initio corporation 3 table of contents 1. introduction:.................................................................................................................. .......................................... 6 1.1 feature summary.................................................................................................................... 6 1.2 firmware/software support .................................................................................................. 7 1.3 devices support............................................................................................................ ......... 7 2. INIC-1608 bloc k diagram:....................................................................................................... .............................. 8 3. pin-out diagram: ............................................................................................................... ..................................... 9 4. pin signal description: (48-pin package)....................................................................................... ....................... 10 4.1 usb interface .............................................................................................................. ........ 10 4.2 sata interface (analog pins) ............................................................................................ 10 4.3 system interface ........................................................................................................... ....... 10 4.4 miscellaneous interface.................................................................................................... ... 10 4.5 nvram interface ............................................................................................................ ... 11 4.6 gpio interface............................................................................................................. ........ 11 4.7 power regulator pins.................................................................................................. ........ 11 4.8 power/gnd .................................................................................................................. ....... 11 5. register addr ess mapp ing: ...................................................................................................... ............................. 12 5.1 general registers.......................................................................................................... ....... 12 5.2 buffers .................................................................................................................... ............. 12 5.3 usb control registers ...................................................................................................... .. 13 5.4 sata control registers..................................................................................................... . 13 5.5 data buffer................................................................................................................ ...... 13 5.6 usb registers...................................................................................................................... 13 5.7 data space mapping......................................................................................................... ... 14 5.8 code space: internal rom: ................................................................................................ 14 6. programming guide: ............................................................................................................. ................................ 15 6.1 cpu write nvram............................................................................................................ ...................................... 15 6.2 cpu read nvram............................................................................................................. ...................................... 15 6.3 cpu poll nvram............................................................................................................. ........................................ 15 6.4 host read/write 8051 data space from usb .......................................................................... 15 6.5 nvram download from usb cab le ........................................................................................ 16 7. register desc riptions: ........................................................................................................................................... 17 7.1 buffer reset register (0x40a3) ..................................................................................... 17 7.2 test control register (0x40a6) .......................................................................................... 17 7.2.0 test control register (0x40a7) .......................................................................................... 17 7.2.1 led_spd register (0x40ac).............................................................................................. 17 7.2.2 miscen register (0x40ad) ................................................................................................ 18 7.3 miscctl register (0x40af): this 8 -registers is in lclk dom ain (37.5 mhz)......................... 18 7.4 softrst register (0x40b0).................................................................................................... 18 7.5 dma flush register (0x40b1)............................................................................................. 18 7.6 usb channel set/clear register (0x40b2 set) (0x40b3 clear) .......................................... 18 7.7 dir/d2ben register (0x40b4) ............................................................................................. 19 7.8 run register (0x40b5) ......................................................................................................... 19 7.9 sata config register (0x40b6) ........................................................................................... 19 7.10 sata reset register (0x40b7)............................................................................................ 20 INIC-1608 initio corporation 4 7.11 i2c_addr register (0x40e0)............................................................................................. 20 7.12 i2c_data register (0x00xe1) (i2c data port).................................................................. 20 7.13 i2c_ctrl register (0x40e2) (i2c control code) .............................................................. 20 7.14 i2c_comm register (0x40e3 ) ........................................................................................ 20 7.15 i2c_status register (0x40e4) ........................................................................................... 21 7.16 otb_counter register (0x40e8)...................................................................................... 21 7.16.1 otb_ctrl register (0x40e9 ) ...................................................................................... 21 7.16.2 otb_int_enable register (0x40ea ) ....................................................................... 21 7.17 usb_int_enable register (0x40f0).................................................................................. 21 7.18 sata_int_enable register (0x40f2)............................................................................. 22 7.19 sata_busy_int register (0x40f3) ............................................................................. 22 7.20 gpio_p_int_enable register (0x40f4).......................................................................... 23 7.21 gpio_n_int_enable register (0x40f5) ......................................................................... 23 7.22 buffer clear register (0x40f7)......................................................................................... 23 7.23 gpio_enable register (0x40f8)....................................................................................... 23 7.24 gpio_data register (0x40f9) .......................................................................................... 23 7.25 gpio_output_enable register (0x40fa)......................................................................... 23 7.26 usb clear register (0x40fb)........................................................................................... 24 7.27 buffer address map ............................................................................................................ 24 7.28 usb control ............................................................................................................... ......... 24 8. sata channel register s (0x4800- 0x483f): ........................................................................................ .... 24 8.1 command parameter blocks (cpb) structu re definition................................................... 24 8.1.1. ata error shadow........................................................................................................ ...... 24 8.1.2. ata status shadow ....................................................................................................... ..... 25 8.1.3. control flags ........................................................................................................... ............ 25 8.1.4. reserved .............................................................................................................................. 25 8.1.5. ata feature shadow ...................................................................................................... .... 25 8.1.6. ata extended feature shadow .......................................................................................... 25 8.1.7. ata device/head shadow ................................................................................................. 25 8.1.8. ata sector count shadow ................................................................................................. 25 8.1.9. ata extended sector count shadow ................................................................................. 26 8.1.10. ata sector number shadow............................................................................................ 26 8.1.11. ata extended sector number shadow............................................................................ 26 8.1.12. ata cylinder low shadow.............................................................................................. 26 8.1.13. ata extended cylinder low shadow.............................................................................. 26 8.1.14. ata cylinder high shadow ............................................................................................. 26 8.1.15. ata extended cylinder high shadow ............................................................................. 26 8.1.16. ata command shadow ................................................................................................... 26 8.1.17. ata control shadow........................................................................................................ 27 8.2 sata phy low control register (4820h) ........................................................................ 27 8.3 sata phy highcontro l register (4821h) ......................................................................... 27 8.4 sata phy low status register (4822h) ........................................................................... 27 8.5 sata phy high status register (4823h) .......................................................................... 27 8.6 sata status register (4830h-4833h)................................................................................. 27 8.7 sata error register (4834h-4837h) .................................................................................. 28 8.8 sata control register (4838h-483bh).............................................................................. 28 8.9 bist mode register (483ch)................................................................................................ 28 INIC-1608 initio corporation 5 8.10 sata_busy_drq_status(483dh)............................................................................................. 28 8.11 bist_act_fis_0 register (483eh)........................................................................................ 28 8.12 bist_act_fis_1 register (483fh)........................................................................................ 28 8.13 bist_act_fis_2 register (4840h) ........................................................................................ 28 8.14 bist_act_fis_3 register (4841h) ........................................................................................ 28 8.15 bist_act_fis_4 register (4842h) ........................................................................................ 28 8.15 bist_act_fis_5 register (4843h) ........................................................................................ 29 8.16 bist_act_fis_6 register (4844h) ........................................................................................ 29 8.17 bist_act_fis_7 register (4845h) ........................................................................................ 29 8.18 bist_act_fis_8 register (4846h) ........................................................................................ 29 9. data buffer: ................................................................................................................... ................................... 29 10. usb regi sters: ................................................................................................................. ..................................... 29 10.1 device status (dev_status[7:0], 0x6020) ............................................................................. 29 10.2 function address (funct_adr[7:0], 0x6021) ........................................................................ 29 10.3 test mode (test_mode[7:0], 0x6022)................................................................................... 30 10.4 end point tx data length low bytes (ep_txlength[7:0], 0x6025) .................................. 30 10.5 end point tx data length high bytes (ep_txlength[15:8], 0x6026) ............................... 30 10.6 end point 0 status/control (ep0_status [7:0], 0x6030: set, 0x6031: clear) ....................... 30 10.7 end point 0 status/control2 (ep0_status2 [7:0], 0x6032: set, 0x6033: clear, bulk-in) .... 30 10.8 end point tx data length low bytes (ep0txlength [7:0], 0x6034) ................................. 31 10.9 setup packet (hdr0?hdr7 [7:0], 0x6038?0x603f) ........................................................... 31 10.10 end point 1 status/control (ep1_status [7:0], 0x6040: set, 0x6041: clear, bulk-in) ...... 31 10.11 end point 2 status/control (ep2_status [7:0], 0x6050: set, 0x6051 clear, bulk-out) ... 31 10.12 usb_rxlength (usb_rxlength[7:0], 0x6052, bulk-out) ................................................... 32 10.13 end point 3 status/control (ep3_status [7:0], 0x6060: set, 0x6061: clear, int r-in) .... 32 10.14 end point tx data length low bytes (ep3txlength [7:0], 0x6062) ............................... 32 10.15 total count0 (totalcnt[7:0], 0x6070 totalcnt0) ............................................................... 32 10.16 total count1 (totalcnt[15:8], 0x6071 totalcnt1) ............................................................. 32 10.17 total count2 (totalcnt[23:16], 0x6072 totalcnt2) ........................................................... 32 10.18 total count3 (totalcnt[31:24], 0x6073 totalcnt3) ........................................................... 32 10.19 load total count (load totalcnt, 0x6074)........................................................................ 33 10.20 global total count0 (gtotalcnt[7:0], 0x6080 gtotalcnt0) ............................................. 33 10.21 global total count1 (gtotalcnt[15:8], 0x6081 gtotalcnt1) ........................................... 33 10.22 global total count2 (gtotalcnt[23:16], 0x6082 gtotalcnt2) ......................................... 33 10.23 global total count3 (gtotalcnt[31:24], 0x6083 gtotalcnt3) ......................................... 33 11. electrical in formation: .......................................................................................................................................... 33 11.1 absolute maximum ratings................................................................................................ 33 11.2 recommended operating conditions.................................................................................. 33 11.3 general dc characteristics ................................................................................................ . 33 11.4 dc electrical characteristics for 3.3v operation ............................................................... 34 INIC-1608 initio corporation 6 1. introduction: the INIC-1608 provides an advanced solution to connect sata devices to usb host with integrated c pu and embedded sram/rom. to provide high performance and cost effective solution, the INIC-1608 integrates usb-phy, ma ss storage class bulk-o nly usb function, sata link/phy core and microprocessor into a single asic. the INIC-1608 provides the data transfer rate of up to 60 mb/sec connecti ng to a 1.5g sata interface. 1.1 feature summary ? integrates usb2.0 phy ip core. ? data transfer rate of up to 60 mb/sec. ? integrated internal turbo 8051 up with 12kb embedded rom and 2kb sram. ? external nvram supported. ? support hid. ? up to 8 gpio pins. ? only one external crystal. ? supports sata (bridged sata) hard disk drives, cd-rw devices, dvds, removable media devices, bd (blu- ray disc) drive ? usb 1.1 and usb 2.0 compliant. ? usb mass storage class bulk-only transport specification compliant. ? sata specification 1.0, sata ii co mpliant (hot plug is supported). ? support ata/atapi device dma and pio mode. ? 2k bytes of data buffer for data transfer. ? on-chip 3.3v to 1.8v regulator and 5v to 3.3v regulator. ? 48 pin lqfp INIC-1608 initio corporation 7 1.2 firmware/software support ? usb mass storage class bu lk-only transport support ? provide software utilities for nvram upgraded. 1.3 devices support ? hard disk drives ? cd-rw devices ? dvds ? re movable media devices ? blu-ray disk driver INIC-1608 initio corporation 8 2. INIC-1608 block diagram: figure1: usb to sata bridge block diagram disk rom 12 kbytes sata control block i2c interface nvram 2k-bits usb phy usb core usb port sata transport layer sata link layer sata phy command buffers registers data buffer (2k bytes) data flow control up8051 INIC-1608 initio corporation 9 3. pin-out diagram: | | | | | | | | | | | | g v p p p s s t t t v g n 3 1 o 1 d c e e e 1 n d 3 | r | a k s s s 8 d 7 s 4 t t t t 0 1 2 p1_2 --- 1 p1_1 --- 2 p1_0 --- 3 v18 --- 4 gnd --- 5 rext --- 6 vd33p --- 7 dp --- 8 dm --- 9 vs33p --- 10 vddu --- 11 p3_0 --- 12 36 --- v33 35 --- v18 34 --- v18 33 --- gnd 32 --- tx0p 31 --- tx0n 30 --- gnd 29 --- v18 28 --- gnd 27 --- rx0n 26 --- rx0p 25 --- v18 v g r r g r r g x x g r 3 n v v n v v n t t n s 3 d 5 3 d 1 3 d a a d a i 3 8 3 l l t o o i o i a | | | | | | | | | | | | 1 1 1 1 1 1 1 2 2 2 2 2 3 4 5 6 7 8 9 0 1 2 3 4 4 4 4 4 4 4 4 4 4 3 3 3 8 7 6 5 4 3 2 1 0 9 8 7 INIC-1608 INIC-1608 initio corporation 10 4. pin signal descript ion: (48-pin package) 4.1 usb interface signal name pin number i/o driver type description dp 8 i/o usb high /full speed buffer (d+) high/full speed d+ signal dm 9 i/o usb high/full speed buffer (d-) high/full speed d- signal rext_usb 6 a power pll voltage reference. current source for 330 ohm(1%) resistor connected to avss 4.2 sata interface (analog pins) signal name pin number i/o driver type description tx0p (sata device) 32 o sata differential transmit positive signal line tx0n (sata device) 31 o sata differential transmit negative signal line rx0p (sata device) 26 i sata differential receive positive signal line rx0n (sata device) 27 i sata differential receive negative signal line xtali 39 i px1r crystal oscillator input (25mhz) xtalo 40 o crystal oscillator output rsata 37 i external reference resister (6.19 k ohm) 4.3 system interface signal name pin number i/o driver type description porst 16 i schmitt-trigger power on reset. active low 4.4 miscellaneous interface signal name pin number i/o driver type description testmode[2:0] 22,21,20 i internal pulldown 77kohm? 312kohm test mode select 000: normal 001: rom-bist 010: tstpdo control by cpu 011: tstpdo monitor rom addr 111: usb phy test 100: sata phy test 101: scan test 110: mbist test INIC-1608 initio corporation 11 4.5 nvram interface signal name pin number i/o driver type description sda/ p1.6 18 i/o internal pullup 94kohm? 261kohm 1. nram data input/output. 2. this pin also configured as p1.6 if nvram is not used. sck/ p1.5 19 i/o internal pullup 94kohm? 261kohm 1. nvram clock. 2. this pin also configured as p1.5 if nvram is not used 4.6 gpio interface signal name pin number i/o driver type description led/p1.7 15 i/o internal pullup 94kohm? 261kohm led: sata activity indicator. can be used as up8051 port 1.7 p3.0/vbus 12 i/o schmitt-trigger up8051 i/o port 3.0, can be used as vbus detection p1.4 17 i/o internal pullup 94kohm? 261kohm up8051 i/o port 1.4, can be used as gpios otb input if enable otb p1.2 1 i/o internal pullup 94kohm? 261kohm up8051 i/o port 1.2, can be used as output gpio p1.1 2 i/o internal pullup 94kohm? 261kohm up8051 i/o port 1.2, can be used as output gpio p1.0 3 i/o internal pullup 94kohm? 261kohm up8051 i/o port 1.0, can be used as gpios 4.7 power regulator pins signal name pin number i/o driver type description rv33i 42 i reg 3.3v input rv18o 43 o reg 1.8v output gnd 44,41 i ground for 2 regulators rv5i 46 i reg 5v input rv33o 45 o reg 3.3v output 4.8 power/gnd signal name pin number i/o driver type description v33 14,48 2 pins (digital 3.3v) for core v18 4,23 2 pins (digital 1.8v) for core gnd 5,13,24,47 4 pins vd33p 7 for usb (3.3v) vs33p 10 for usb (gnd) vddu 11 for usb (1.8v) v33 36 for sata(3.3v) v18 25,29,34,35 for sata(1.8v) gnd 28,30,33,38 for sata(gnd) INIC-1608 initio corporation 12 5. register address mapping: 5.1 general registers address read value write value 40a3h bufferrst bufferrst 40a6h testctl testctl 40a7 testctl1 testctl1 40ach led_spd led_spd 40adh miscen miscen 40afh miscctl miscctl 40b1h dmaflush dmaflush 40b2h usb channel set usb channel set 40b3h usb channel clear usb channel clear 40b4h dir/d2ben dir/d2ben 40b5h run run 40b6h sata config sata config 40b7h sata reset sata reset 40b8h satastatus na 40e0h i2c_addr[7:0] i2c_addr[7:0] 40e1h i2c_data i2c_data 40e2h i2c_ctrl i2c_ctrl 40e3h i2c_comm i2c_comm 40e4h i2c_status - 4040 otb_counter[7:0] otb_counter[7:0] 40e9h otb_ctrl[7:0] otb_ctrl[7:0] 40eah otb_int_en otb_int_en 40f0h usbint_en usbint_en 40f2h sataint_en sataint_en 40f4h gpio_p_int_en gpio_p_int_en 40f5h gpio_n_int_en gpio_n_int_en 40f7h buffer clear buffer clear 40f8h gpioen gpioen 40f9h gpiodatain gpiodataout 40fah gpioouten gpioouten 40fbh usb clear usb clear 5.2 buffers address read value write value 4100h-413fh (64 bytes) control_in buffer can?t be written by cpu 4140h-417fh (64 bytes) cbw_in buffer cbw_in buffer 41c0h-41ffh (64 bytes) control_out buffer control_out buffer 4240h-427fh (64 bytes) csw_out buffer csw_out buffer 4280h-423fh (64 bytes) hid_out buffer hid_out buffer INIC-1608 initio corporation 13 5.3 usb control registers address read value write value 4500h-450fh usb control usb control 5.4 sata control registers address read value write value 4800h reserved reserved 4801h ata error shadow ata error shadow 4802h ata status shadow ata status shadow 4803h control flag control flag 4804h-480fh reserved reserved 4810h ata feature shadow ata feature shadow 4811h ata extended feature shadow ata extended feature shadow 4812h ata device/head shadow ata device/head shadow 4813h reserved reserved 4814h ata sector count shadow ata sector count shadow 4815h ata extended sector count shadow ata extended sector count shadow 4816h ata sector number shadow ata sector number shadow 4817h ata extended sector number shadow ata extended sector number shadow 4818h ata cylinder low shadow ata cylinder low shadow 4819h ata extended cylinder low shadow ata extended cylinder low shadow 481ah ata cylinder high shadow ata cylinder high shadow 481bh ata extended cylinder high shadow ata extended cylinder high shadow 481ch ata command shadow ata command shadow 481dh ata control shadow ata control shadow 4820h sata phy control [7:0] sata phy control [7:0] 4821h sata phy control [15:8] sata phy control [15:8] 4822h sata phy status [7:0] sata phy status [7:0] 4823h sata phy status [15:8] sata phy status [15:8] 4830h-4833h sata status sata status 4834h-4837h sata error sata error 4838h-483bh sata control sata control 483ch-483fh sata active sata active 5.5 data buffer address read value write value 5000h-57ffh data buffer data buffer 5.6 usb registers address read value write value 6020h dev_status dev_status 6021h funct_adr funct_adr 6022h test_mode test_mode 6025h eptxlength[7:0] eptxlength[7:0] 6026h eptxlength[15:8] eptxlength[15:8] 6030h ep0_status ep0_ control (set) INIC-1608 initio corporation 14 6031h ep0_status ep0_ control (clear) 6032h ep0_status2 ep0_ control 2(set) 6033h ep0_status2 ep0_ control 2(clear) 6034h ep0txlength ep0txlength 6038-603f hdr0-7 - 6040h ep1_status ep1_ control (set) 6041h ep1_status ep1_ control (clear) 6050h ep2_status ep2_ control (set) 6051h ep2_status ep2_ control (clear) 6052h usb_rxlength[7:0] - 6060h ep3_status ep3_ control (set) 6061h ep3_status ep3_ control (clear) 6070h totalcnt0 totalcnt0 6071h totalcnt1 totalcnt1 6072h totalcnt2 totalcnt2 6073h totalcnt3 totalcnt3 6074h - loadtotalcnt 6080h gtotalcnt0 gtotalcnt0 6081h gtotalcnt1 gtotalcnt1 6082h gtotalcnt2 gtotalcnt2 6083h gtotalcnt3 gtotalcnt3 5.7 data space mapping mapping address type access type mapping block 0000h-07ffh data read/write internal sram (2kb) 4000h-47ffh data read/write internal register/buffers 4800h-48ffh data read/write sata registers 5000h-57ffh data read/write data buffer (2kb) 6000h-60ffh data read/write usb registers 5.8 code space: internal rom: address read value write value 0-3000h firmware code (12k bytes) (instruction fetch) n/a INIC-1608 initio corporation 15 6. programming guide: 6.1 cpu write nvram. 1. cpu write access address at register i2c_addr(0x40e0). 2. cpu write data at register i2c_data(0x40e1). 3. cpu write control code at register i2c_ctrl(0x40e2). 4. cpu write run and read_write direction(0) at register i2c_comm(0x40e3). 5. cpu poll i2c_comm bit 7, wait until cleared. 6. cpu may read register i2c_status( 0x40e4) to check write success or not. 6.2 cpu read nvram. 1. cpu write access address at register i2c_addr(0x40e0). 2. cpu write control code at register i2c_ctrl(0x40e2). 3. cpu write run and read_write direction(1) at register i2c_comm(0x40e3). 4. cpu poll i2c_comm bit 7, wait until cleared. 5. cpu read register i2c_data(0x40e1). 6. cpu may read register i2c_status(0x40e4) to check read success or not. 6.3 cpu poll nvram. after write data to nvram, nvram need certain tim e before next write operation can be accepted. cpu may poll nvram to decide nvram ready or not. it is done same as a nvram read. if i2c_status(0x40e4) bit 0 is 1, the nvram not ready. 6.4 host read/write 8051 data space from usb 1. host send read_chip_id packet through control channel to read chip-id, which is 0x29c5_1608 here. default hardware report pid is 0x160f. 2. host send hold_cpu packet through control channel to set hold_cpu bit. 3. host may send data_write/data_read packet through control channel to write/read 8051 data space. data_write setup packet format is, offset field size value description 0 bmreqtype 1 0x40 vendor write 1 breq 1 0x81 data space write 2 addr[7:0] 3 wvalue 2 addr[15:8] address to be writen 4 data[7:0] data space data 5 windex 2 0x00 don?t care 6 0x00 7 wlength 2 0x00 data_read setup packet format is, offset field size value data description INIC-1608 initio corporation 16 0 bmreqtype 1 0xc0 vendor read 1 breq 1 0x82 data read 2 addr[7:0] 3 wvalue 2 addr[15:8] address to be writen 4 0x00 don?t care 5 windex 2 0x00 don?t care 6 0x01 7 wlength 2 0x00 data from data space read_chip_id setup packet format is: offset field size value data description 0 bmreqtype 1 0xc0 vendor read 1 breq 1 0x03 2 0x00 3 wvalue 2 0x00 4 0x00 don?t care 5 windex 2 0x00 don?t care 6 0x04 7 wlength 2 0x00 chip-id 0x08, 0x16, 0xc9, 0x25 hold_cpu setup packet format is: offset field size value description 0 bmreqtype 1 0x40 vendor write 1 breq 1 0x04 hold_cpu 2 0x00 3 wvalue 2 0x00 don?t care 4 0x00 don?t care 5 windex 2 0x00 don?t care 6 0x00 don?t care 7 wlength 2 0x00 don?t care 6 .5 nvram download from usb cable the download utility may read/write nvram thro ugh access i2c registers similar as cpu does. 1. host send read_chip_id packet through control channel to read chip-id, which is 0x29c5_1608 here. default hardware report pid is 0x160f. 2. host send hold_cpu packet through control channel to set hold_cpu bit. 6.5.1 nvram write. 3. host send data_write packet with wvalue i2c_addr(0x40e0) and windex[15:8] the nvram address to be accessed 4. host send data_write packet with wvalue i2c_data(0 x40e1) and windex[15:8] the value to be write to nvram 5. host send data_write packet with wvalue i2c_ctrl(0x40e2) and windex[15:8] the control code to be write to nvram 6. host send data_write packet with wvalue i2c_comm(0x40e3) and windex[15:8] the run bit[b7] and read/write direction 0 [b0] INIC-1608 initio corporation 17 7. host poll bit 7 of i2c_comm(0x40e3) until this bit is cleared by sending data_read packet with wvalue i2c_comm(0x40bf) 8. host send data_read packet with wvalue i2 c_status(0x40e4) to check write success or not 6.5.2 nvram read. 9. host send data_write packet with wvalue i2c_addr(0x40e0) and windex[15:8] the nvram address to be accessed 10. host send data_write packet with wvalue i2c_ctrl(0x40e2) and windex[15:8] the control code to be write to nvram 11. host send data_write packet with wvalue i2c_comm(0x40e3) and windex[15:8] the run bit[b7] and read/write direction 1 [b0] 12. host poll bit 7 of i2c_comm(0x40e3) until this bit is cleared by sending data_read packet with wvalue i2c_comm(0x40e3) 13. host send data_read packet with wvalue i2c_data(0x40e1) to get the data from nvram. 14. host send data_read packet with wvalue i2 c_status(0x40e4) to check write success or not 6.5.3 nvram polling. just same as nvram read. if i2c_status(0x40e4) bit 0 is 1, nvram not ready for next write. 7. register descriptions: 7.1 buffer reset register (0x40a3) field name rscu bit # reset description reserved r 7-1 7?b0 reserved. buffer0rst rw 0 1?b0 dma buffer 0 reset. this bit is used to reset dma bu ffer 0. this bit is self-cleared by hardware after set. 7.2 test control register (0x40a6) field name rscu bit # reset description reserved r 7-5 3?b0 reserved. chipid r 4 1?b0 chip-id. read only. 1-> 1608 0-> 1606 testmuxsel rw 3-0 4?h0 test mux out put select. these 4 bits select specific internal signals to be routed to device?s outputs during test mode. (internal testing purpose) 7.2.0 test control register (0x40a7) field name rscu bit # reset description se0_en rw 7 1?b0 reserved. revid r 6:3 1?b0 rev-id. squ_b rw 2-0 3?b1 11 sata phy control reserved 7.2.1 led_spd register (0x40ac) field name rscu bit # reset description out_abort_en rw 7 1?b0 0->enable out abort usbatadone_en rw 6 1?b0 1-> enable usbatad one clear internal counter cpuclkswitch_en rw 5 1?b0 0-> cpu clock is 75mhz 1-> cpu clock is 10mhz(150mhz/16) usb_wakeupen rw 4 1?b0 1: enable external interrupt wakeup usb when device is now in suspend INIC-1608 initio corporation 18 state. led_spd [3 : 0] rw 3-0 4?h0 define led blink speed : 0000 : 1/32 sec. per blink 0001 : 2/32 sec. per blink up to ~ ~ 1111 : 16/32 sec. per blink 7.2.2 miscen register (0x40ad) field name rscu bit # reset description force_usbmode r 7 1?b0 1-> set usbmode start_calib1_en rw 6 1?b0 1 : allow sata oob to do calibra tion for sata host channel ivbus_sel_en r 5 1?b0 1->enable internal vbus re-rounting tl_wakeup rw 4 1?b0 control bit for sata block tl_slumber rw 3 1?b0 control bit for sata block tl_partial rw 2 1?b0 control bit for sata block sata_busy_sel rw 1 1?b0 0 : select sata_busy as sata device activity detection 1 : select (sata_busy or sata_drq ) as sata device activity detection reserved r 0 1?b0 reserved-for sata 7.3 miscctl register ( 0x40af): this 8-registers is in lclk domain (37.5 mhz) field name rscu bit # reset description usb_crystal_en rw 7 1?b0 1->turn off usb clock bp_sel rw 6 1?b1 0: select usb mode 1: select sata-to- sata bypass mode. usb_clk_ctl rw 5 1?b0 firmware set/clr this bit. if set, phy clock is free run. if clr, phy clock will stop when device goes to suspend mode. usb_enumeration rw 4 1?b1 1: enable usb enumeration. 0: disable usb enumeration. hw_rst_event rw 3 1?b1 this bit is set by hardware reset. software reset has no effect on this bit. firmware can clear this bit by writing a 0 to it. hiden rw 2 1?b0 1 : endpoint defined as: 8(in), 2(out), 1(int) 0 : endpoint defined as: 1(in), 2(out), 3(int) newmode rw 1 1?b0 1 : 1608 report residue same as totalcnt minus usb txed or rxed 0 : 1608 report residue same as totalcnt minus ata txed or rxed ivbus rw 0 1?b0 the value of vbus is equivalent this bit if ivbus_sel_en(0x40ad[5]) is set. 7.4 softrst register (0x40b0) field name rscu bit # reset description reserved r 7-1 7?b0 reserved. softrst w 0 1?b0 1: software reset (setting this bit will reset the data buffer related logic) 7.5 dma flush register (0x40b1) field name rscu bit # reset description sgbufcpurd rw 7 1?b0 f/w read sgbuf in fifo mode, f/w set this bit first. reserved r 6-1 6?b0 reserved flush/abort rw 0 1?b0 when dma buffer is overrun, this bit is used by firmware to flush data out for outgoing data or abort the dma operation for incoming data. this bit is self-cleared by hardware. 7.6 usb channel set/clear regist er (0x40b2 set) (0x40b3 clear) field name rscu bit # reset description reserved r 7 7?b0 reserved INIC-1608 initio corporation 19 cmdtx4run (for hid_out) rwu 6 1?b0 the set register is set by software and cleared by hardware when transfer is completed. when the clear register is set by software, the corresponding channel is cleared. cmdtx3run (for csw_out) rwu 5 1?b0 the set register is set by software and cleared by hardware when transfer is completed. when the clear register is set by software, the corresponding channel is cleared. reserved r 4 1?b0 reserved cmdtx1run (for control_out) rwu 3 1?b0 the set register is set by software and cleared by hardware when transfer is completed. when the clear register is set by software, the corresponding channel is cleared. reserved r 2-0 3?b0 reserved 7.7 dir/d2ben register (0x40b4) field name rscu bit # reset description dir rw 7 1?b0 indicates the di rection of the data transfer: 0: data write into sata device. 1: data output from sata device. proper dir bit must be programmed before writing ata command d2ben rw 6 1?b0 data to buffer mode enable. the two sata channels can be configured to transfer data to and fr om the buffer memory without a host connection. reserved r 5-0 6?b0 reserved 7.8 run register (0x40b5) field name rscu bit # reset description phaseerror rws 7 1?b0 phase error status. set by hardware. reserved r 6-1 6?b0 reserved run rw 0 1?b0 write 1: start the data transfer; the hardware will clear this bit when the transfer is completed. firmware also can write 0 to clear this bit. d2ben (register 0x40b4 bit 6) and run (register 0x40b5 bit 0) work together to start di fferent data transfer: d2ben run 0 0 : idle 0 1 : start transfer between usb and sata device according to the dir bit ( register 0x40b4 bit 7 ) . 1 0 : idle 1 1 : start transfer between dma buffer and sata device according to the dir bit ( register 0x40b4 bit 7 ) 7.9 sata config register (0x40b6) field name rscu bit # reset description hwflushen rw 7 1?b1 when set to 1: automatic hardware flush is enabled. phaseerren rw 6 1?b1 when set to 1: an phaseerr event will report phaseerr to register 0x40b5 bit 7. led_idle_high rw 5 1?b0 0: sata idle will drive led pin low 1: sata idle will drive led pin high INIC-1608 initio corporation 20 led_busy_sel rw 4 1?b0 0 : sata busy will blink led 1 : sata busy will drive led on reserved r 3-0 4?b0 reserved 7.10 sata reset register (0x40b7) field name rscu bit # reset description ataphyrst rw 7 1?b0 sata channels hard reset to phy layer, auto-clear by hardware reserved r 6-5 2?b0 reserved. ataupprst rw 4 1?b0 sata channel 0 re set to link/transport/application layer reserved r 3-1 3?b0 reserved. atach0int r 0 1?b0 sata channel 0 interrupt signal. 7.11 i2c_addr register (0x40e0) field name rscu bit # reset description i2c_addr rw 7-0 8?h0 cpu writes the to-be executed nvram address to this register. 7.12 i2c_data register (0x00xe1) (i2c data port) field name rscu bit # reset description i2c_data rw 7-0 8?h0 this is th e data port for cpu to access nvram a: to write to nvram: cpu writes a 8-bit data to this port, hardware will send this data to nvram b: to read from nvram: cpu reads this port to get data from nvram 7.13 i2c_ctrl register (0x40e2) (i2c control code) field name rscu bit # reset description reserved w 7 1?b0 reserved control_code rw 6:3 4?b0 control code block_select rw 2:0 3?b0 i2c device block select bits 7.14 i2c_comm register (0x40e3 ) field name rscu bit # reset description i2c_tx_start rw 7 1?b0 1-> hardware start to read/write nvram. clear by hardware when finished. reserved rw 6:1 6?b0 reserved rd_nwr wr 0 1?b0 0-> write to nvram 1-> read data from nvram INIC-1608 initio corporation 21 7.15 i2c_status register (0x40e4) field name rscu bit # reset description reserved rw 7-3 5?b0 reserved data_ack r 0 1?b0 0-> nvram ack with data write phase 1->nvram nack with data write phase addr_ack r 0 1?b0 0-> nvram ack with address write phase 1->nvram nack with address write phase ctrl_ack r 0 1?b0 0-> nvram ack with contrl code write phase 1->nvram nack with contrl code write phase 7.16 otb_counter register (0x40e8) field name rscu bit # reset description otb_counter rw 7:0 8?b0 how many pu sh-release done. clear after fw read. 7.16.1 otb_ctrl register (0x40e9 ) field name rscu bit # reset description i2c_enable rw 7 1?b0 0-> i2c enable 1-> i2c disable, sck(pin 21) as 8051 port 1.5 sda(pin 20) as 8051 port 1.6 otb_enbale rw 6 1?b0 0-> otb enable, 8051 port 1.4 as button input 1-> otb disable, 8051 port 1.4 as gpio reserved rw 5:2 4?b0 reserved debouncing time rw 1:0 2?b0 2?b00-> 36ms 2?b01->72ms 2?b10->108ms 2?b11->144ms 7.16.2 otb_int_enable re gister (0x40ea ) field name rscu bit # reset description otb_counter_inte rw 7 1?b0 1: enable otb_counter<>0 trigger sysint. otb_pos_inte rw 6 1?b0 1: enable button release trigger sysint otb_neg_inte rw 5 1?b0 1: enable button push trigger sysint reserved rw 4:0 5?b0 reserved 7.17 usb_int_enable register (0x40f0) field name rscu bit # reset description usb_busrst_int_en rw 7 1?b0 1: enable usb_busrst to trigger sysint. to check if this int has occurred, please read register 6030 bit 6. usb_bulkonlyrst_int _en rw 6 1?b0 1: enable usb_bulkonlyrst to trigger sysint. to check if this int has occurred, please read register 6030 bit 5. INIC-1608 initio corporation 22 usb_ep0req_int_en rw 5 1?b0 1: enable usb_ ep0req to trigger sysint. to check if this int has occurred, please read register 6032 bit 0. usb_cbw_int_en rw 4 1?b0 1: enable usb_cbw to trigger sysint. to check if this int has occurred, please read register 6050 bit 1. usb_wakeup_int_en rw 3 1?b0 1: enable usb_wakeup to trigger sysint. to check if this int has occurred, please read register 6020 bit 3. (value 0 means wakeup) usb_suspendint_en rw 2 1?b0 1: enable usb_suspend to trigger sysint. to check if this int has occurred, please read register 6020 bit 3. (value 1 means suspend) vbus_p__int_en rw 1 1?b0 1: enable positive of vbus to trigger sysint. to check if this int has occurred, please read register 40af bit 6. (value 1 means vbus is high) vbus_n__int_en rw 0 1?b0 1: enable negative of vbus to trigger sysint. to check if this int has occurred, please read register 40af bit 6. (value 1 means vbus is high) 7.18 sata_int_enable register (0x40f2) field name rscu bit # reset description reserved r 7-4 4?b0 reserved sata_busy_int_en rw 3 1?b0 1: enable sata host detection to trigger sysint sata_dev_int_en rw 2 1?b0 1: enable sata_dev_int to trigger sysint. to check if this int has occurred, please read register 40b7 bit 0. sata_phyrdy_p_in t_en rw 1 1?b0 1: enable positive of sata_phyrdy to trigger sysint. to check if this int has occurred, please read register 4820 bit 0. sata_phyrdy_n_in t_en rw 0 1?b0 1: enable negitive of sata_phyrdy to trigger sysint. to check if this int has occurred, please read register 4820 bit 0. 7.19 sata_busy_int register (0x40f3) field name rscu bit # reset description reserved r 7-4 4?b0 reserved sata_busy_int rw 3 1?b0 ?1? indicates a sysint caused by sata host detection has occurred. firmware can write ?1 ? to clear this status bit. 1. usb to sata mode if this bit set, sata cable was plugged. whenever f/w clear it, this bit will be set periodically unless firmware switches to sata mode. 2. sata to sata mode if this bit set, sata cable was plugged. after the connection between host and device has been built, this bit won?t be set anymore after it was cleared by firmware unless the bus reset has occurred or sata cable has been un-plugged and re-plugged. if squelch bit (0x4822) set is detected, sata cable was unplugged. INIC-1608 initio corporation 23 reserved r 2-0 3?b0 reserved 7.20 gpio_p_int_enable re gister (0x40f4) field name rscu bit # reset description reserved rw 7-4 4?b0 reserved gpio3_p_int_en rw 3 1?b0 1: enable gpio3 high level to trigger sysint. gpio2_p_int_en rw 2 1?b0 1: enable gpio2 high level to trigger sysint. gpio1_p_int_en rw 1 1?b0 1: enable gpio1 high level to trigger sysint. gpio0_p_int_en rw 0 1?b0 1: enable gpio0 high level to trigger sysint. 7.21 gpio_n_int_enable re gister (0x40f5) field name rscu bit # reset description reserved r 7-4 4?b0 reserved gpio3_n_int_en rw 3 1?b0 1: enable gpio3 low level to trigger sysint. gpio2_n_int_en rw 2 1?b0 1: enable gpio2 low level to trigger sysint. gpio1_n_int_en rw 1 1?b0 1: enable gpio1 low level to trigger sysint. gpio0_n_int_en rw 0 1?b0 1: enable gpio0 low level to trigger sysint. 7.22 buffer clear register (0x40f7) field name rscu bit # reset description reserved r 7-1 7?b0 reserved clear buffer rw 0 1?b0 1: clear data buffer and state machine. 7.23 gpio_enable register (0x40f8) field name rscu bit # reset description reserved rw 7-1 7?b0 reserved gpio0 _en rw 0 1?b0 1: use p1_7 pin as gpio0 7.24 gpio_data register (0x40f9) field name rscu bit # reset description reserved rw 7-1 7?b0 reserved gpio0 _data rw 0 1?b0 read: read the value of p1_7 pin (i.e. gpio0_datain) write: write the value to gpio0_dataout (i.e. p1_7 pin) 7.25 gpio_output_enable register (0x40fa) field name rscu bit # reset description reserved rw 7-1 7?b0 reserved gpio0_output_en rw 0 1?b0 0: select gpio0 to input mode 1: select gpio0 to output mode INIC-1608 initio corporation 24 7.26 usb clear register (0x40fb) field name rscu bit # reset description reserved r 7-1 4?b0 reserved clear usb rw 0 1?b0 1: clear usb traffi c problem. (when usb traffic encounter problem) 7.27 buffer address map address description 4100-413fh control_in buffer, 64 bytes 4140-417fh cbw_in buffer, 64 bytes 41c0-41ffh control_out buffer, 64 bytes 4240-426fh csw_out buffer, 48 bytes 4280-42afh hid_out buffer, 48 bytes 7.28 usb control address description 4500-450fh usb control 450eh bit 7-0: datalength[7:0] 450fh bit 7-0: datalength[15:8] 8. sata channel registers (0x4800-0x483f): 8.1 command parameter blocks (cpb) structure definition 31 24 23 16 15 08 07 00 control flag ata status ata error reserved 4800h reserved 4804h reserved 4808h reserved 480ch port sel. ata device/head ata ex. feature ata feature 4810h ata ex. sector number ata sector number ata ex. sector count ata sector count 4814h ata ex. cylinder high ata cylinder high ata ex. cylinder low ata cylinder low 4818h reserved reserved ata control ata command 481ch 8.1.1. ata error shadow offs et: 4801h when the host programs the cpb, this byte of data is ignored. at the end of a command, the idma engine will update the content of this register to reflect the c ontent of the ata error register after status update. bit name definition 07-00 0 ataerr ata error register content. INIC-1608 initio corporation 25 8.1.2. ata status shadow offs et: 4802h when the host programs the cpb, this byte of data is ignored. at the end of a command, the idma engine will update the content of this register to reflect the c ontent of the ata status register after status update. bit name definition 07-00 0 atastat ata status register content. 8.1.3. control flags offset: 4803h bit name definition 7:3 5?b0 pkt_length packet command cdb structure size in bytes. 2:1 2?b0 reserved reserved 0 1?b0 ppkt packet command. when set, indicating the current command is an atapi packet command. after sending the register fis to the device, hardware will automatically fetch the cdb from cmdreceive buffer and send to device through pio. 8.1.4. reserved offset: 4804-4807h 8.1.5. ata feature shadow offs et: 4810h bit name definition 07-00 0 atafeat ata feature register content. 8.1.6. ata extended feature shadow offset: 4811h bit name definition 07-00 0 ataexfeat ata extended feature register content. 8.1.7. ata device/head shadow offs et: 4812h bit name definition 07-00 0 atadevhd ata device/head register content. 8.1.8. ata sector count shadow offs et: 4814h bit name definition 07-00 0 ataseccnt ata sector count register content. INIC-1608 initio corporation 26 8.1.9. ata extended sector count shadow offs et: 4815h bit name definition 07-00 0 ataexseccnt ata extended sector count register content. 8.1.10. ata sector number shadow offset: 4816h bit name definition 07-00 0 atasecnum ata sector number register content. 8.1.11. ata extended sector number shadow offs et: 4817h bit name definition 07-00 0 ataexsecnum ata extended s ector number register content. 8.1.12. ata cylinder low shadow offset: 4818h bit name definition 07-00 0 atacyllo ata cylinder low register content. 8.1.13. ata extended cylinder low shadow offset: 4819h bit name definition 07-00 0 ataexcyllo ata extended cylinder low register content. 8.1.14. ata cylinder high shadow offset: 481ah bit name definition 07-00 0 atacylhi ata cylinder high register content. 8.1.15. ata extended cylinder high shadow offset: 481bh bit name definition 07-00 0 ataexcylhi ata extended cylinder high register content. 8.1.16. ata command shadow offset: 481ch bit name definition 07-00 0 atacmd ata command register content. INIC-1608 initio corporation 27 8.1.17. ata control shadow offs et: 481dh bit name definition 07-00 0 atactl ata control register content. 8.2 sata phy low cont rol register (4820h) field name rscu bit # reset description pw_dn_txpll rw 7 1?b0 power down for tx_pll usb_clk_ctrl rw 6 1?b0 1: set usb clock free run 0: usb clock may stop when device in suspend mode pw_dn_rxpll rw 5 1?b0 power down for rx_pll reserved rw 4 1?b0 reserved bypass_calib rw 3 1?b1 disable calibration process during oob farafleb rw 2 1?b0 place phy in far-end analog loopback mode nearafleb rw 1 1?b0 place phy in near-end analog loopback mode fphyrdy rw 0 1?b0 force phy ready for 8.3 sata phy highcontrol register (4821h) field name rscu bit # reset description reserved rw 15-13 3?b100 reserved drv_level_ch1 rw 12 1?b0 1: select 700mv output drive for channel 1 0: select 500mv output driver for channel 1 pw_dn_ch0 rw 11 1?b0 power down for channel 0 , bias circuit and calibration drv_level_ch0 rw 10 1?b0 1: select 700mv output drive for channel 0 0: select 500mv output driver for channel 0 pw_dn_ch1 rw 9 1?b0 power down for channel 1 tx_pl_err_rst rw 8 1?b0 tx phase error reset 8.4 sata phy low status register (4822h) field name rscu bit # reset description oob_status_1 r 7 1?b0 oob_status_0 r 6 1?b0 when 4bits oob_staus_3~0 is 4?b1010, it means phy is ready, all other states mean not ready reserved r 5:4 2?b0 reserved squelch r 3 1?b0 sata ch0 squelch signal out reserved r 2:0 3?b0 reserved 8.5 sata phy high status register (4823h) field name rscu bit # reset description phystatus[15:10] rw 15-10 6?h0 phy status[15:10] oob_status_3 r 9 oob_status_2 r 8 when 4bits oob_staus_3~0 is 4?b1010, it means phy is ready, all other states mean not ready 8.6 sata status register (4830h-4833h) field name rscu bit # reset description INIC-1608 initio corporation 28 sstatus r 31-0 32?b0 sata status 8.7 sata error register (4834h-4837h) field name rscu bit # reset description serror r 31-0 32?b0 sata error 8.8 sata control regi ster (4838h-483bh) field name rscu bit # reset description scontrol rw 31-0 32?b0 sata control 8.9 bist mode register (483ch) field name rscu bit # reset description bist mode rw 7-6 2?h0 not defined bist mode_5 r/w 5 0 far end loopback pattern will be sent out bist mode_4 r/w 4 0 far end retimed loopback will be sent out bist mode_3 r/w 3 0 lone bit pattern will bet sent out bist mode_2 r/w 2 0 high freq. pattern will be sent out bist mode_1 r/w 1 0 mid freq. pattern will be sent out bist mode_0 r/w 0 0 low freq. pattern will be sent out 8.10 sata_busy_drq_status(483dh) field name rscu bit # reset description sata_busy_drq rw 7-4 4?h0 sata_busy_drq_3 r/w 3 0 dev_busy sata_busy_drq_2 r/w 2 0 dev_drq sata_busy_drq_1 r/w 1 0 ata_dev_busy sata_busy_drq_0 r/w 0 0 ata_dev_drq 8.11 bist_act_fis_0 register (483eh) field name rscu bit # reset description bist_act_fis_0 rw 7-0 8?h0 bist_act_fis data1[7:0] 8.12 bist_act_fis_1 register (483fh) field name rscu bit # reset description bist_act_fis_1 rw 7-0 8?h0 bist_act_fis data1[15:8] 8.13 bist_act_fis_2 register (4840h) field name rscu bit # reset description bist_act_fis_2 rw 7-0 8?h0 bist_act_fis data1[23:16] 8.14 bist_act_fis_3 register (4841h) field name rscu bit # reset description bist_act_fis_3 rw 7-0 8?h0 bist_act_fis data1[31:24] 8.15 bist_act_fis_4 register (4842h) field name rscu bit # reset description INIC-1608 initio corporation 29 bist_act_fis_4 rw 7-0 8?h0 bist_act_fis data2[7:0] 8.15 bist_act_fis_5 register (4843h) field name rscu bit # reset description bist_act_fis_5 rw 7-0 8?h0 bist_act_fis data2[15:8] 8.16 bist_act_fis_6 register (4844h) field name rscu bit # reset description bist_act_fis_6 rw 7-0 8?h0 bist_act_fis data2[23:16] 8.17 bist_act_fis_7 register (4845h) field name rscu bit # reset description bist_act_fis_7 rw 7-0 8?h0 bist_act_fis data2[31:24] 8.18 bist_act_fis_8 register (4846h) field name rscu bit # reset description bist_act_fis_8 rw 7-0 8?h0 bist_act_fis pattern definition write this register will trigger hw to send bist _act_fis (58) out. 9. data buffer: address read value write value 5000h-57ffh data buffer data buffer 10. usb registers: 10.1 device status (dev_status[7:0], 0x6020) field name rscu bit # reset description vbus r 7 1?b0 read: usb?s vbus status test_mode rsu 6 1?b0 set when set_feature (test_mode). attach ru 5 1?b1 hardware reset default state. clear if detect vbus valid. then set power bit powered ru 4 1?b0 set if vbus=1 & previ ous state is attach. or, power interruption. suspend ru 3 1?b0 after bus idle for sometime, ha rdware set this bit. when resume detected, hardware reset this bit and return to previous state default ru 2 1?b0 after bus rese t, hardware set this bit. addressed rscu 1 1?b0 set_addr ess or set_configuration(0) configured rscu 0 1?b0 set_configuration 10.2 function address (funct_adr[7:0], 0x6021) field name rscu bit # reset description rsvd ru 7 1?b0 reserved adr ru 6:0 7?b0 set_address INIC-1608 initio corporation 30 10.3 test mode (test_mode[7:0], 0x6022) field name rscu bit # reset description rsvd ru 7:4 4?b0 reserved test_mode rwu 3:0 4?b0 test mode selectors(table 9-7, usb2.0 spec) 4?h1: test_j 4?h2: test_k 4?h4: test_se0_nak 4?h8: test_packet others: rsvd 10.4 end point tx data length low bytes (ep_txlength[7:0], 0x6025) field name rscu bit # reset description ep_txlength rwu 7:0 8?b0 for ep1 (bulk_in): for ata-command-no-dma-involved, this field indicates how many bytes sent back to host. maximum 512-bytes 10.5 end point tx data length high bytes (ep_txlength[15:8], 0x6026) field name rscu bit # reset description rsvd r 7:2 6?b0 reserved ep_txlength rwu 1:0 2?b0 high bytes 10.6 end point 0 status/control (ep0_sta tus [7:0], 0x6030: set, 0x6031: clear) field name rscu bit # reset description suspend_gnt rsc 7 1?b0 suspend-request granted usb_busrst rcu 6 1?b0 set by hardware after an usb bus reset detected . clear by firmware. bulk_only_rst rcu 5 1?b0 set by hardware, read an d cleared by firmware after firmware responds bulk-only-reset command done. ep0_line_st ru 4:3 2?b0 line states ep0_speed ru 2 1?b0 1?hs, 0--fs remote_wakeup rscu 1 1?b0 set/clr by firmware. remote wakeup request. halt rscu 0 1?b0 1-ep0 halt. function stall. device reset is require to clear this bit 10.7 end point 0 status/control2 (ep0_status2 [7:0], 0x6032: set, 0x6033: clear, bulk-in) field name rscu bit # reset description fw_rdy rsc 7 1?b0 0: default value as no firmwa re installed. hardware response all control packets for firmware download in most cases. 1: firmware controls some setup packet response. rsvd r 6:4 3?b0 reserved ep0_statrun rsu 3 1?b0 set by firmware if devi ce ready to go to control status stage. ep0_out rcu 2 1?b0 set by hardware if a control co mmand-data is received. clear by firmware after processing. ep0_run rsu 1 1?b0 set by firmware. when firmware se t this bit, the data will be transferred from data buffer to usb. how many bytes transferred is based on the data transfer INIC-1608 initio corporation 31 length in the ep_txlength( 0x25, 0x26) ep0_setup rcu 0 1?b0 set by hardware if a contro l command is received. clear by firmware after processing. 10.8 end point tx data length low bytes (ep0txlength [7:0], 0x6034) field name rscu bit # reset description rsvd r 7 1?b0 reserved ep0txlength rwu 6:0 7?b0 for ep0 (control): this fi eld is filled by firmware . when firmware taking control setup packet response, firmware write this fiel d to inform hardware the data length to be send back to host. maximum 64-bytes. 10.9 setup packet (hdr0?hdr7 [7:0], 0x6038?0x603f) field name rscu bit # reset description hdr ru 7:0 8?bx 8 bytes setup packet. 10.10 end point 1 status/control (ep1_status [7 :0], 0x6040: set, 0x6041: clear, bulk-in) field name rscu bit # reset description gtotalcnteq 0 r 7 0 1? ata global total counter equal 0 0--- ata global total counter not equal 0 totalcnteq0 r 6 0 1? ata total counter equal 0 0--- ata total counter not equal 0 short_in r 5 1?b0 1-> the last sent packet is a short packet. for bulk-in packet only cbw_err r 4 1?b0 1-> indicate a wrong cbw received csw_run rscu 3 1?b0 set by firmware when firmware ready to send csw. clear by hardware after csw is sent successfully. rsvd r 2 1?b0 reserved ep1_run rscu 1 1?b0 set by firmware. when firmware se t this bit, the data will be transferred from data buffer to usb. how many bytes transferred is based on the data transfer length in the ep_txlength( 0x25, 0x26) halt rscu 0 1?b0 1-ep1 halt. 10.11 end point 2 status/control (ep2_status [7:0], 0x6050: set, 0x6051 clear, bulk-out ) field name rscu bit # reset description fs_en rw 7 1?b0 force device to full speed only mode rx_2k rsc 6 1?b0 1-> bridge rxed 2k bytes. auto-clear after rxed cbw short_out r 5 1?b0 1-> the last received packet is a short packet. for bulk-out packet only rx_done rsc 4 1?b0 1->bridge received all data from host. ready for csw transmit. auto-clear after rxed cbw rx_tokenin rw 3 1?b0 1-> in-token re ceived. auto-clear after rxed cbw ep2_rx rcu 2 1?b0 set by hardware after the bulk out packet received. th e number of total data length received will be shown in usb_rxl ength register. this bit is used by firmware to monitor the data transfer between usb and internal data buffer. this bit is cleared by firmware or automatically cleared by hardware after the INIC-1608 initio corporation 32 next cbw received or sg0r un bit set by firmware. ep2_cbw rcu 1 1?b0 set by hardware if a valid cbw received. clear after processing by firmware. halt rscu 0 1?b0 1-ep2 halt. 10.12 usb_rxlength (usb_rxlength[7:0], 0x6052, bulk-out) field name rscu bit # reset description rxlength ru 7:0 8?b0 the low byte of data length r eceived. this register is used to show how many date received from usb to internal data buffer. 10.13 end point 3 status/control (ep3_status [7 :0], 0x6060: set, 0x6061: clear, intr-in) field name rscu bit # reset description rsvd r 7:3 5?b0 reserved ep3_run rsu 2 1?b0 1?packet ready. cleared by hardware after tx completed rsvd r 1 1?b0 reserved halt rscu 0 1?b0 1-ep3 halt. 10.14 end point tx data length low bytes (ep3txlength [7:0], 0x6062) field name rscu bit # reset description rsvd r 7 1?b0 reserved ep3txlength rwu 7:0 7?b0 for ep3 (int_in): this field is filled by firmware. firmware writes this field to inform hardware the data length to be sent back to host. maximum 64- bytes. 10.15 total count0 (totalcnt[7:0], 0x6070 totalcnt0) field name rscu bit # reset description totalcnt0 rwu 7-0 8?b0 totalcnt[7:0] 10.16 total count1 (totalcnt[15:8], 0x6071 totalcnt1) field name rscu bit # reset description totalcnt1 rwu 7-0 8?b0 totalcnt[15:8] 10.17 total count2 (totalcnt[23:16], 0x6072 totalcnt2) field name rscu bit # reset description totalcnt2 rwu 7-0 8?b0 totalcnt[23:16] 10.18 total count3 (totalcnt[31:24], 0x6073 totalcnt3) field name rscu bit # reset description totalcnt3 rwu 7-0 8?b0 totalcnt[31:24] INIC-1608 initio corporation 33 10.19 load total count (load totalcnt, 0x6074) field name rscu bit # reset description reserved r 7-1 7?b0 reserved loadtotalcnt w 0 1?b0 write an 1 to this bit will re-load the value from register 0x73-0x70?s totalcnt[31:0] to internal counter. 10.20 global total count0 (gtotalcnt[7:0], 0x6080 gtotalcnt0) field name rscu bit # reset description gtotalcnt0 rwu 7-0 8?b0 gtotalcnt[7:0] 10.21 global total count1 (gtotalcnt[15:8], 0x6081 gtotalcnt1) field name rscu bit # reset description gtotalcnt1 rwu 7-0 8?b0 gtotalcnt[15:8] 10.22 global total count2 (gtotalcnt[23:16], 0x6082 gtotalcnt2) field name rscu bit # reset description gtotalcnt2 rwu 7-0 8?b0 gtotalcnt[23:16] 10.23 global total count3 (gtotalcnt[31:24], 0x6083 gtotalcnt3) field name rscu bit # reset description gtotalcnt3 rwu 7-0 8?b0 gtotalcnt[31:24] 11. electrical information: 11.1 absolute maximum ratings symbol parameter min max units vcc power supply -0.3 3.6 v vin input voltage -0.3 vcc+0.3 v vout output voltage -0.3 vcc+0.3 v tstg storage temperature -55 150 c 11.2 recommended operating conditions symbol parameter min typ max units vcc power supply 3.0 3.3 3.6 v vin input voltage 0 - vcc v tj commercial junction operating temperature 0 25 115 c 11.3 general dc characteristics symbol parameter min typ max units iil input leakage current -1 1 a ioz tristate leakage current -1 1 a cin input capacitance 2.8 pf INIC-1608 initio corporation 34 cout output capacitance 2.7 4.9 pf cbid bi-directional buffer capacitance 2.7 4.9 pf 11.4 dc electrical characterist ics for 3.3v operation (under vcc=3.0-3.6v, tj=0-115c) symbol parameter conditions min typ max units vil input low voltage cmos -0.3 0.8 v vih input high voltage cmos 2.0 5.5 v vol output low voltage ioh-2-24ma 0.4 v voh output high voltage ioh=2-24ma 2.4 v ri input pullup/pulldown resistance vil=0/vih=vcc 75 k icc operating supply current vcc=3.3v 150 ma 12. packaging specification 2005.09.06 a3 4 lqfp48 (7x7mm) package outline footprint 2.0mm 10 : 1 1 of 1 |
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